In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.

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In the past several decades, the most popular fault model used in practice is the single stuck-at fault model. This page was last edited on 23 Novemberat This allows using a relatively simple vector matrix to quickly test all the comprising FFs, as well as to trace failures to specific FFs.

The ATPG process for a targeted fault consists of two phases: Second, it is possible that a detection pattern exists, but the algorithm cannot find one. Historically, ATPG has focused on a set of faults derived from a gate-level fault model. Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity. ATPG is a topic that is covered by several conferences throughout the year.

The single stuck-at fault model is structural because it is defined based on a structural gate-level circuit model. The classic example of this is a redundant circuit, designed such that no single fault causes the output to change.

These metrics generally indicate test quality higher with more fault detections and test application time higher with more patterns.

Any single fault from the set of equivalent faults can represent the whole set. Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others.


Automatic test pattern generation

This model is used to describe faults for CMOS logic gates. The combinational ATPG method allows testing the individual nodes or flip-flops of the logic circuit without being concerned with the operation of the overall circuit. ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test full scansynchronous sequential, or asynchronous sequentialthe level of abstraction used to represent the circuit under test gate, register-transfer, switchand the required test quality.

Equivalent faults produce the same faulty behavior for all input patterns. First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault. For designs that are sensitive to area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.

In such a circuit, any single fault will be inherently undetectable. A fault model is a mathematical description of how a defect alters design behavior.

Therefore, many different ATPG methods have been developed to address combinational and sequential circuits. In the latter case, dominant driver keeps its value, while the other one gets the AND or OR value of its own and the dominant driver.

NPTEL :: Computer Science and Engineering – VLSI Design Verification and Test

However, according to reported results, no single strategy or heuristic out-performs others for all applications or circuits. A fault atg said to be detected by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output.

The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure failure analysis [1]. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques atpt be needed.

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ATPG can xtpg to find a test for a particular fault in at least two cases. Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault through the space of all possible test vector sequences.

During test, a so-called scan-mode is enabled forcing all flip-flops FFs to be connected baics a simplified fashion, effectively bypassing their interconnections as intended during normal operation.

Automatic test pattern generation – Wikipedia

By using this site, you agree to the Terms of Use and Privacy Policy. This observation implies that a test generator should include a comprehensive set of heuristics.

However, these test generators, combined with low-overhead DFT techniques such as partial scanhave shown a certain degree of success in testing large designs. A defect is an error caused in a device during the manufacturing process. In stuck-short, a transistor behaves as it is always conducts or stuck-onand stuck-open is when a transistor never conducts current tapg stuck-off.

Retrieved from ” https: The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. Views Read Edit View history. From Wikipedia, the free encyclopedia. As design trends move toward nanometer technology, new manufacture testing problems are emerging. Removing equivalent faults from entire set of faults is called fault collapsing.

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